Optimizing dominant time constant in RC circuits

We propose to use the dominant time constant of a resistor-capacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, speci cally, semide nite programs (SDPs). For example, assuming that the conductances and capacitances are a ne functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeo surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with non-grounded capacitors. Second, it always results in convex optimization problems for which very e cient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing. Research supported in part by AFOSR (under F49620-95-1-0318), NSF (under ECS-9222391 and EEC9420565), MURI (under F49620-95-1-0525), and a gift from Synopsys.